1. Technical Field
The present invention relates in general to a configuration of a test system for testing integrated circuits (ICs) on a wafer. More particularly, the present invention relates to the configuration of components of a probe card used in the wafer test system.
2. Related Art
When building semiconductor wafer contactor test systems, a major obstacle is the resource restrictions of a wafer tester. The tester typically does not have enough resources or test channels to test all Devices Under Test (DUT) on a wafer. Because of the variety of numbers of DUTs on wafers, a given tester will likely be used both as a full wafer contact probe type interface, and an interface which contacts a portion of the wafer, referred to as a partial wafer probe.
With an increased number of test channels, as well as increased size of wafers and the number of DUTs on a wafer, it becomes more desirable to modify the probe card for connecting the tester to a wafer to enable testing more ICs at one time in a low cost efficient manner. Larger probe cards are desired with more probes to connect to and test more DUTs at one time. Even with smaller sized wafers, it was desirable for probe cards to support more probes so that all DUTs on a wafer can be tested with less touch downs of the probe card. The added probes on a probe card, however, result in more complex routing of electrical lines, and more complex systems for alignment of the probe card relative to a wafer being tested.
FIG. 1 shows a block diagram of a test system using a probe card for testing DUTs on a semiconductor wafer. The test system includes a test controller 4 connected by a communication cable 6 to a test head 8. The test system further includes a prober 10 made up of a stage 12 for mounting a wafer 14 being tested, the stage 12 being movable to contact the wafer 14 with probes 16 on a probe card 18. The prober 10 includes the probe card 18 supporting probes 16 which contact DUTs formed on the wafer 14.
In the test system, test data is generated by the test controller 4 and transmitted through the communication cable 6, test head 8, probe card 18, probes 16 and ultimately to DUTs on the wafer 14. Test results are then provided from DUTs on the wafer back through the probe card 18 to the test head 8 for transmission back to the test controller 4. Once testing is complete, the wafer is diced up to separate the DUTs.
Test data provided from the test controller 4 is divided into the individual tester channels provided through the cable 6 and separated in the test head 8 so that each channel is carried to a separate one of the probes 16. The channels from the test head 8 are linked by connectors 24 to the probe card 18. The probe card 18 then links each channel to a separate one of the probes 16.
FIG. 2 shows a cross sectional view of components of the probe card 18. The probe card 18 is configured to provide both electrical pathways and mechanical support for the spring probes 16 that will directly contact the wafer. The probe card electrical pathways are provided through a printed circuit board (PCB) 30, an interposer 32, and a space transformer 34. Test data from the test head 8 is provided through pogo pins or zero insertion force (ZIF) connectors 24 typically connected around the periphery of the PCB 30. Channel transmission lines 40 distribute signals from the tester interface connectors (pogo or ZIF) 24 horizontally in the PCB 30 to contact pads on the PCB 30 to match the routing pitch of pads on the space transformer 34. The interposer 32 includes a substrate 42 with spring probe electrical contacts 44 disposed on both sides. The interposer 32 electrically connects individual pads on the PCB 30 to pads forming a land grid array (LGA) on the space transformer 34. The LGA pad connections are typically arranged in a regular multi-row pattern. Transmission lines 46 in a substrate 45 of the space transformer 34 distribute or “space transform” signal lines from the LGA to spring probes 16 configured in an array. The space transformer substrate 45 is typically constructed from either multi-layered ceramic or organic based laminates. The space transformer substrate 45 with embedded circuitry, probes and LGA is referred to as a probe head.
Mechanical support for the electrical components is provided by a back plate 50, bracket (Probe Head Bracket) 52, frame (Probe Head Stiffener Frame) 54, leaf springs 56, and leveling pins 62. The back plate 50 is provided on one side of the PCB 30, while the bracket 52 is provided on the other side and attached by screws 59. The leaf springs 56 are attached by screws 58 to the bracket 52. The leaf springs 56 extend to movably hold the frame 54 within the interior walls of the bracket 52. The frame 54 then includes horizontal extensions 60 for supporting the space transformer 34 within its interior walls. The frame 54 surrounds the probe head and maintains a close tolerance to the bracket 52 such that lateral motion is limited.
Leveling pins 62 complete the mechanical support for the electrical elements and provide for leveling of the space transformer 34. The leveling pins 62 are adjusted so that brass spheres 66 provide a point contact with the space transformer 34. The spheres 66 contact outside the periphery of the LGA of the space transformer 34 to maintain isolation from electrical components. Leveling of the substrate is accomplished by precise adjustment of these spheres through the use of advancing screws 62, referred to as the leveling pins. Leveling pins 62 are adjustable to level the space transformer 34 and assure all the probes 16 will make contact with a wafer. The leveling pins 62 are screwed through supports 65 in the back plate 50. Motion of the leveling pin screws 62 is opposed by leaf springs 56 so that spheres 66 are kept in contact with the space transformer 34. The leaf springs 56 are designed to be much stronger than the interposer 32, so that raising and lowering the leveling screws 62 is opposed by the leaf springs 56 and the springs 42 and 44 of the interposer 32 serve only to assure electrical contact is maintained between the space transformer 34 as it moves relative to the PCB.
FIG. 3 shows an exploded assembly view of components of the probe card of FIG. 2. FIG. 3 shows attachment of the back plate 50, PCB 30, and bracket 52 using two screws 59. Four leveling screws 62, are provided through the back plate 50 and PCB 30 to contact four spheres 66 near the corners of the space transformer substrate 34. The frame 54 is provided directly over the space transformer substrate 34, the frame 54 fitting inside the bracket 52. The leaf springs 56 are attached by screws 58 to the bracket 52. Two screws 58 are shown for reference, although additional screws 58 (not shown) are provided around the entire periphery to attach the leaf springs.
FIG. 4 shows a perspective view of the opposing side of PCB 30 illustrating the arrangement of connectors 24 around its periphery. In FIG. 3, the connectors 24 of the PCB 30 are facing down and not shown. In typical probe cards, the connectors 24 (typically zero insertion force (ZIF) connectors) provide connections located around the periphery of the probe card, and are configured to mate with connectors that are typically arranged in a similar fashion on the test head. Although illustrated as flexible cable ZIF connectors, other connector types may be used, such as pogo pins, non-ZIF flexible cable connectors, conductive elastomer bumps, stamped and formed spring elements, etc.